When transmitting a plurality of data bits in parallel over a respective plurality of parallel transmission lines, differences in transmission line length and/or other transmission line characteristics may cause the plurality of data bits to be received at different times. Stated in other words, different ones of the parallel transmission lines may have different transmission line delays. Accordingly, data training may be used to tune a timing of transmission of the plurality of data bits to compensate for the different transmission line delays so that reception of the plurality of data bits may be improved. More particularly, a phase (or delay) of data transmission over each of the parallel transmission lines may be tuned relative to a clock signal to compensate for different transmission line delays.
By way of example, data input/output pads of a memory controller and an associated integrated circuit (IC) memory device may be electrically coupled using respective data input/output lines (also referred to as data input/output transmission lines). During a data training operation, a plurality of data training write operations are performed using known data transmitted from the memory controller in parallel over the parallel data input/output transmission lines at a plurality of different transmission phases (or transmission delays/advances). After each of the data training write operations, a determination is made for each of the data bits transmitted in parallel over each of the parallel input/output transmission lines whether the write operation for each data bit was a pass or a fail at the integrated circuit memory device, and a transmission phase (or delay) relative to the clock is selected for each data input/output transmission line resulting in a successful (i.e., a passing) data training write operation.
If multiple transmission phases (or delays) result in successful (i.e., passing) data training write operations over a same data input/output transmission line, a middle of the phases (or delays) resulting in successful (i.e., passing) data training write operations may be selected. Stated in other words, if more that two phases (or delays) result in successful (i.e., passing) data training write operations for a data input/output transmission line, an intermediate (or center) one of the successful (or passing) phases may be selected for that data input/output transmission line for subsequent write operations. Accordingly, neither the least nor the greatest phase/delay resulting in a successful data training write operation is selected if a plurality of phases/delays result in successful data training write operations.